Thin film transistor, circuit device and liquid crystal display

ABSTRACT

A thin film transistor includes a one conductive type semiconductor layer; a source region and a drain region which are separately provided in the semiconductor layer; and a gate electrode provided above or below the semiconductor layer with an insulating film interposed therebetween, wherein the width of the junction face between the source region and the channel which is provided between the source region and drain region, is different from the width of the junction face between the above channel region and the drain region.

BACKGROUND OF THE INVENTION

1. Related Applications

This application claims priority from International Application No.PCT/JP03/002511, filed Mar. 4, 2003, which claims priority of JapanesePatent Application No. 2002-82451, filed on Mar. 25, 2002.

2. Field of the Invention

The present invention relates to a thin film transistor, a circuitapparatus including the thin film transistor, a liquid crystal displayincluding the thin film transistor, and a liquid crystal displayincluding the circuit apparatus.

3. Description of Prior Art

A thin film transistor (referred to as “TFT” hereinafter) is used as,for example, a switching device for a pixel of a liquid crystal display,a component device for a peripheral circuit apparatus and so forth.

The TFT includes an active layer made of a one conductive type formedsemiconductor. This active layer includes a source region as well as adrain region, both of which are formed by doping a part of thesemiconductor of the active layer with high concentrated impurities. Agate electrode is formed above or below a channel region with a gateinsulating film interposed therebetween, the channel region beinglocated between these source and drain regions.

As the active layer, for example, an n-channel type polycrystallinesilicon film (Poly-Si film) is used.

So far, when forming a plurality of TFTs including an active layerhaving a source region and a drain region, on a sheet of substrate,there has been caused such a problem that the electrical properties ofeach TFT becomes uneven due to the difference in the grain size and theplane direction in each grain in the active layer. Accordingly, as ameans of solving this problem, it is required to enlarge the grain size.

With regard to a method of enlarging the grain size in a semiconductorlayer directly or indirectly formed on a sheet of substrate, somereports have been already made(e.g., see to Non-Patent Document 1).However, it is not possible to control the crystal orientation in thein-plane direction of the semiconductor layer by means of thesetechniques as disclosed.

There are some reports reporting that unevenness in the electricalproperty of a circuit apparatus including TFTs depends on the aforesaidcrystal orientation (e.g., see Non-Patent Document 2 as shown later).This will be described referring to FIG. 15.

FIG. 15 is a schematic plan view for indicating an example of grains andgrain boundaries in an active layer made of semiconductor in a prior artTFT.

In FIG. 15, there is shown a part of a semiconductor film in which, 100denotes a grain of semiconductor, 101 a grain boundary, 102 an activelayer, and 103 the flow direction of electric current flowing in theactive layer 102, respectively. The active layer 102 is a layer made ofone conductive type formed semiconductor.

The electrical property of the TFT varies depending on the number of thegrains 100 or grain boundaries 101 in the active layer 102. When theelectric current flows in the direction as shown by an arrow 103 passingthrough the active layer 102 including a lot of grain boundaries 101,the number of times the electric current goes across the grainboundaries 101 varies from TFT to TFT. Accordingly, there is caused sucha problem that the electrical property of each TFT formed on a sheet ofsubstrate can not become uniform.

In case of forming a TFT including such an active layer that is formedby using a part of the aforesaid Poly-Si film as the active layer 102,as it is not possible to control the crystal orientation of each silicongrain 100 in the active layer, it is so difficult to reduce theunevenness in the electrical property due to the different planedirection. Especially, when the channel length is small, as theoccupation rate that one grain 100 occupies the active layer 102 becomeslarge, there is caused such a problem that it is not possible to lessenthe unevenness in the electrical property of the prior art TFT.

Furthermore, there are some papers reporting that the unevenness in theelectrical property of each TFT like this is caused by that the grainboundary 101 forms a high potential barrier height in the active layer102 made of polycrystalline silicon, thereby lowering the field-effectmobility of the TFT (e.g., see Non-Patent Document 3).

The grain boundary 101 standing in the direction crossing the movingdirection of electron or hole as a carrier of electric charge and thegrain boundary 101 standing in the almost same direction as the movingdirection give different influence to the electrical property of theTFT, respectively.

As a result, even if the TFT is formed on an identical substrate, thereis caused such a problem that the electrical property of the TFT becomesdifferent.

Non-Patent Document 1: Masakiyo Matsumura “Preparation of Ultra-LargeGrain Silicon Thin-Films by Excimer-Laser” (Journal of The SurfaceScience Society of Japan, “Surface Science,” Vol. 21, No. 5, pp. 278–287(pp. 34–43), 2000, The Surface Science Society of Japan).

Non-Patent Document 2: Bernd Goebel et al., Electron Devices, IEEETransactions, Vol. 48, No. 5, pp.897–905, May 2001.

Non-Patent Document 3: Levinson et al., Journal of Applied Physics, Vol.53, No. 2, pp. 1193–1202, February 1982.

Non-Patent Document 4: Research And Development Association For FutureElectron Devices Incorporated Foundation, “Research And DevelopmentProject on Three-Dimension Integrated Circuit,” pp. 87–104, Oct. 23,1991.

SUMMARY OF THE INVENTION

An object of the invention is to provide a TFT, a circuit apparatusincluding the TFT, a liquid crystal display including the TFT, and aliquid crystal display including the circuit apparatus, the unevennessin the electrical property of all the above-mentioned TFTs being madeless.

A semiconductor device according to the invention includes a substrate;a one conductive type semiconductor layer provided on the substrate andhaving a sectorial or trapezoidal shape of which an opening angle is 20degrees or more; and a transistor provided on the one conductive typesemiconductor layer. According to the invention, there becomes small theunevenness in the field-effect mobility of the transistor.

A TFT according to the invention includes a one conductive typesemiconductor layer; a source region and a drain region which areseparately provided in the semiconductor layer; and a gate electrodeprovided above or below the semiconductor layer with an insulating filminterposed therebetween, wherein the width of the junction face betweenthe source region and a channel region that is provided between thesource region and the drain region, is different from the width of thejunction face between the channel region and the drain region.

According to the invention, it is possible to obtain such an effect thatthe unevenness in the field-effect mobility of the TFT becomes small.

It is preferable that the semiconductor layer has an approximatelytrapezoid or approximately sector plane shape.

It is preferable that the trapezoid or sector plane shape has an openingangle of 20 degrees or more. In the trapezoid, the opening angle is anangle made by two non-parallel lines.

It is preferable that the semiconductor layer includes one or more grainboundaries, which extend in the direction from the source region to thedrain region or from the drain region to the source region of thesemiconductor layer.

It is preferable that the semiconductor layer includes two or more grainboundaries, each of which extends in the direction from the sourceregion to the drain region or from the drain region to the source regionof the semiconductor layer and also, each of which extends in thein-plane direction of the semiconductor layer in correspondence with theopening angle of the trapezoid or sector.

It is preferable that the semiconductor layer includes two or more grainboundaries, each of which extends in the direction from the sourceregion to the drain region or from the drain region to the source regionof the semiconductor layer, and also, two grain boundaries adjacent toeach other extend in the in-plane direction of the semiconductor layerwith an opening angle.

It is preferable that the semiconductor layer includes two or more grainboundaries, each of which extends in the direction from the sourceregion to the drain region or from the drain region to the source regionof the semiconductor layer, and also, two grain boundaries adjacent toeach other are in parallel with the in-plane direction of thesemiconductor layer.

It is preferable that the difference between two angles is 20 degrees ormore, one of the two angles being an angle made by one imaginary lineconnecting the middle position of the width of the junction face betweenthe channel region and source region with the middle position of thewidth of the junction face between the channel region and the drainregion and the other imaginary line extending in the extending directionof the grain boundary, and the other angle being an opening angledefined by the width of the junction face between the channel region andthe source region and the width of the junction face between the channelregion and the drain region.

A circuit apparatus according to the invention includes a substrate; aTFT formed directly or indirectly on the substrate, the TFT being ofN-type; and a TFT formed directly or indirectly on the substrate, theTFT being of P-type, wherein the TFT of N-type and the TFT of P-type arearranged to take point-symmetrical positions, respectively.

A liquid crystal display according to the invention includes theaforesaid TFT.

The other crystal liquid display according to the invention includes theaforesaid circuit apparatus.

The other circuit apparatus includes a substrate; a semiconductor filmhaving a lot of grain boundaries and provided on the substrate; and aTFT which is formed in the semiconductor film, and in which electriccurrent flows in parallel with the direction of one of the grainboundaries.

The other circuit apparatus includes a substrate; a semiconductor filmprovided on the substrate and having a lot of grain boundaries; and aplurality of TFTs which are formed in the same crystal orientation ofthe semiconductor film and in which electric current flows in parallelwith the direction of each of the grain boundaries.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 shows the schematic constitution of a TFT and another TFTaccording to the embodiment 1 of the invention, wherein (a) indicates aplan view showing the schematic constitution of a TFT according to theembodiment 1 of the invention, (b) indicates a sectional view of (a),(c) indicates a plan view showing the schematic constitution of anotherTFT according to the embodiment 1, and (d) indicates a sectional view of(c).

FIG. 2 shows an illustration for explaining an experiment carried out toexamine a relation between an angle as made by the center axis and the(001) direction of the sectorial crystal in a circular semiconductorfilm and the change of the field-effect mobility when varying theopening angle of the sector.

FIG. 3 is a graph showing the orientation dependence of the field-effectmobility as obtained from the experiment as explained in connection withFIG. 2, wherein there is shown the relation between the orientation ofthe center axis A of the sectorial crystal and the relative mobility atan opening angle θ of the sectorial shape.

FIG. 4 is a schematic plan view showing the schematic shape of an activelayer according to the embodiment 1 and the opening angle of the sector.

FIG. 5 shows illustrations of grain boundaries, wherein (a) through (d)are schematic plan views showing grain boundaries in respective activelayers.

FIG. 6 shows illustrations of circular semiconductor films, wherein (a)is a schematic plan view showing a circular semiconductor film includingradially extending grain boundaries and (b) is a schematic plan viewshowing an example of arrangement of the active layer in the circularsemiconductor film.

FIG. 7 is a schematic plan view showing TFTs according to the embodiment1.

FIG. 8 shows illustrations of the manufacturing process of the TFTaccording to the embodiment 1, wherein (a) through (g) are schematicsectional views showing the manufacturing process of the TFT accordingto the embodiment 1.

FIG. 9 shows illustrations of the manufacturing process of the TFTaccording to the embodiment 1, wherein (h) through (o) are schematicsectional views showing the manufacturing process of the TFT accordingto the embodiment 1.

FIG. 10 shows illustrations of the manufacturing process of the TFTaccording to the embodiment 1, wherein (p) through (u) are schematicsectional views showing the manufacturing process of the TFT accordingto the embodiment 1.

FIG. 11 shows illustrations of a complementary type circuit apparatusaccording to the embodiment 2 of the invention, wherein (a) is a planview showing the complementary type circuit apparatus according to theembodiment 2 of the invention and (b) is a circuit diagram thereof.

FIG. 12 shows illustrations of the manufacturing process of acomplementary type circuit apparatus according to the embodiment 2 ofthe invention, wherein (a) and (b) are schematic sectional views showingthe manufacturing process of the complementary type circuit apparatusaccording to the embodiment 2 of the invention.

FIG. 13 shows illustrations of the embodiment 3 according to theinvention, wherein (a) is a schematic perspective view indicating alaser irradiation method different from FIGS. 8( c), and (b) is aschematic plan view showing the grain resulting from the above methodaccording to the embodiment 3 of the invention.

FIG. 14 shows illustrations of long and slender grains, wherein (a) is aschematic plan view showing long and slender grains in which a pluralityof grain boundaries extend in parallel, (b) is a schematic plan viewshowing various examples on the arrangement of the active layer in longand slender grains.

FIG. 15 is a schematic plan view for explaining an example of grains andgrain boundaries in the active layer made of semiconductor in a priorart TFT.

PREFERRED EMBODIMENT OF THE INVENTION

Some embodiments of the invention will now be described in detail withreference to the accompanying drawing. In the figures referred to forexplanation of the invention, a thing having like function is denotedwith a like numeral or sign and the repetitive explanation thereaboutwill be omitted.

An active layer formed to decrease the unevenness in the electricalproperty of a TFT depending on the plane direction of the semiconductorof which the active layer made, has an approximately trapezoid (referredto as “trapezoidal” hereinafter) plane shape or an approximately sector(referred to as “sectorial” hereinafter) plane shape. A semiconductorlayer as formed such that an opening angle of the trapezoidal orsectorial shape exceeds a certain angle, has an advantage in that thereare averaged various plane direction of crystals or grains in thesemiconductor. “Opening angle” of aforesaid trapezoid indicates an anglemade by two non-parallel straight lines thereof.

When using a part of a polycrystalline silicon film including largegrains as well as radially extending grain boundaries, for example, apart of a flat circular polycrystalline silicon film as the activelayer, for example, the following advantage is attainable. As will bedescribed later, by forming an N-type TFT in the first sectorial activelayer and forming a P-type TFT in the second sectorial active layer tomake them be point-symmetrically arranged within a one grain so as torelatively face to each other, it becomes possible to make up acomplementary type circuit apparatus (referred to as “CMOS apparatus”hereinafter) having more excellent complementarity comparing with theprior art one. TFTs, CMOS apparatuses, diodes, transistors and so forthmay be formed in the trapezoidal or sectorial semiconductor layer.

The relation between the opening angle of the aforesaid sector and theaforesaid mobility has been examined referring to the study on the planedirection of the semiconductor crystal and the field-effect mobility,which is disclosed in the non-patent document 2.

FIG. 2 shows an illustration for explaining an experiment carried out toexamine a relation between an angle as made by the center axis and the(001) direction of the sectorial crystal and the change of thefield-effect mobility when varying the opening angle of the sector, inletting a apart of the semiconductor such as the aforesaidpolycrystalline silicon film the active layer.

In FIG. 2, 1 indicates an approximately circle (referred to as“circular” hereinafter) semiconductor film, 2 a sectorial crystal, A thecenter axis of a sectorial crystal, B (001) direction, θ the openingangle of the sector, and C an angle made by the center axis A of thesectorial crystal and the (001) direction B.

FIG. 3 is a graph showing the orientation dependence of the field-effectmobility as obtained from the aforesaid experiment. There is shown therelation between the orientation of the center axis A of the sectorialcrystal and the relative mobility at an opening angle θ of the sector.

As shown in FIG. 3, when the opening angle θ of the sector (FIG. 2) islarge, unevenness of the aforesaid mobility is small. That is, when thecenter axis A of the sectorial crystal (FIG. 2) deviates from the (001)direction B, there is hardly seen difference in the aforesaid mobility.Besides, when letting the center axis A of the sectorial crystal be the(001) direction B, if the other direction is included, the unevennessbecomes small. As will be understood from FIG. 3, unevenness of theaforesaid mobility is in the range of approximately 5% or less whenletting the opening angle θ of the sector be 20 degrees or more.

That is, when the active layer in which the TFT is formed has asectorial shape of which the opening angle θ is 20 degrees or more,unevenness in the mobility of the electrical property of the TFT isadequately small even if there is unevenness in the crystal orientationof the semiconductor (e.g., silicon,) in the active layer.

The aforesaid TFT includes the active layer made of semiconductor and agate electrode which is directly or indirectly formed above or below theactive layer so as to occupy at least a part of it. The active layer hasa channel region located below or above the gate electrode layer, and asource region and a drain region which are located on the both sideportions in the channel region.

Let an angle made by two imaginary lines Lm and Lg be α (referred to as“angle regarding the transistor direction” hereinafter), the former Lmconnecting the middle position of the width of the junction face of thechannel region and the source region with the middle position of thewidth of the junction face of the channel region and the drain regionand the latter Lg extending in the direction that the grain boundaryextends. Besides, let an opening angle defined by the width of thejunction face of the channel region and the source region and the widthof the junction face of the channel region and the drain region be β.When the active layer includes one or more grain boundaries, by locatingthe active layer such that the difference between α and β is 20 degreesor more, the electrical property of the TFT becomes good and unevennessin the electrical property becomes well.

Besides, if an N-type TFT formed in the first sectorial active layer anda P-type TFT formed in the second sectorial active layer arepoint-symmetrically arranged within a one grain such that theyrelatively face to each other, the electrical properties of those TFT'sbecome equal to each other, and as described later, it becomes possibleto obtain a complementary type circuit apparatus with complementarity asexpected at the stage of designing it.

Embodiment 1

FIG. 1( a) is a plan view showing the schematic constitution of a TFTaccording to the embodiment 1, FIG. 1( b) is a sectional view of FIG. 1(a), FIG. 1( c) is a plan view showing the schematic constitution ofanother TFT according to the embodiment 1, and FIG. 1( d) is a sectionalview of FIG. (c).

In FIG. 1, 10 denotes a TFT, 11 an active layer made of one conductivetype semiconductor, for example, an n-type silicon (Si) having anapproximately trapezoid plane shape, 12 a source region formed by dopingthe semiconductor layer 11 with high concentrated impurities, 13 a drainregion formed by doping the semiconductor layer 11 with highconcentrated impurities, 14 a gate electrode provided above a channelregion 16 located between the source region 12 and the drain region 13,and 15 a gate insulating film.

Also, in FIG. 1, 17 denotes the direction where the source region 12 andthe drain region 13 are formed (referred to as “source-drain direction17”). W_(s) denotes the width of the junction face between the channelregion 16 and the source region 12. In other words, W_(s) indicates thewidth of the source region 12 in the vicinity of the end portion of thegate electrode 14 (including the width in the same direction). W_(d)denotes the width of the junction face between the channel region 16 andthe drain region 13. In other words, W_(d) indicates the width of thedrain region 13 in the vicinity of the end portion of the gate electrode14. The source-drain direction 17 indicates the flowing direction ofcarriers from the source region 12 to the drain region 13 (i.e. channeldirection).

In the embodiment 1, in the TFT including the source region 12 and thedrain region 13 which are in the active layer 11 made of semiconductorand the gate electrode 14 formed above or below the channel region 16located between the source region 12 and the drain region 13, the widthW_(s) of the junction face between the channel region 16 and the sourceregion 12 in the vicinity of the end portion of the gate electrode 14 isdifferent from the width W_(d) of the junction face between the channelregion 16 and the drain region 13 in the vicinity of the end portion ofthe gate electrode 14.

That is, W_(s)>W_(d) (in FIGS. 1( a) and 1(b)) while W_(s)<W_(d) (inFIGS. 1( c) and 1(d)).

The active layer 11 has an approximately trapezoid or approximatelysector plane shape. These approximately trapezoid and approximatelysector shapes include a shape satisfying the relation of W_(s)>W_(d) orW_(s)<W_(d).

In case of providing the gate electrode 14 below the active layer 11,the same explanation as made above will be applicable to it except thatthe gate electrode 14 is formed below the active layer 11 with the gateinsulating film interposed therebetween, thus omitting an illustrationsrelated thereto.

In FIG. 4, there are shown a schematic shape of the trapezoidal activelayer 11 according to the embodiment 1 and a schematic plan view showingthe opening angle θ of the trapezoidal shape.

In the embodiment 1, as shown in FIG. 4, the trapezoidal or sectorialactive layer 11 has the opening angle θ of 20 degrees or more. As hasbeen already explained referring to FIGS. 2 and 3, the more directionsother than the direction the center axis A are included, the smaller theunevenness in the field effect mobility becomes. Accordingly, when theopening angle θ of the aforesaid trapezoidal shape is 20 degrees ormore, the unevenness of the aforesaid field-effect mobility is in therange of approximately 5% or less, thus the unevenness in the electricalproperties of TFTs becoming small. The same thing can be said withregard to the sectorial active layer.

FIGS. 5( a) through 5(d) are schematic plan views showing grainboundaries 21 in respective trapezoidal active layers 11.

FIGS. 5( a) and 5(b) show grain boundaries 21 in the trapezoidal activelayers 11 according to the embodiment 1. For comparison, FIGS. 5( c) and5(d) show grain boundaries 21 in the active layers 11 according to theprior art.

In the embodiment 1, as shown in FIGS. 5( a) and 5(b), the active layer11 is arranged such that the source-drain direction 17 of the relevantactive layer 11 approximately coincides with the direction of grainboundaries in the relevant active layer 11.

In the embodiment 1, as shown in FIGS. 5( a) and 5(b), the boundaries 21exist in the direction approximately parallel to the source-draindirection 17, that is, the moving direction of electron and hole ascarrier of the electric charge. Consequently, as any potential barriercaused by the grain boundaries 21 can not exist in the carrier movingdirection, the electrical property of the TFT becomes good. Contrary tothis, as shown in FIGS. 5( c) and 5(d), when the grain boundaries 21exist so as to intersect the source-drain direction 17, the electriccurrent amount is influenced by the number of potential barriers causedby the grain boundaries 21, thereby the electrical property of the TFTbecomes not good.

FIG. 6( a) is a schematic plan view showing a circular semiconductorfilm 1 including grain boundaries 21 which radially extend and FIG. 6(b) is a schematic plan view showing an example of arrangement of theactive layers 11 a through 11 e in the circular semiconductor film 1.

22 indicates the direction of electric current flowing in each of theactive layers 11 a through 11 e.

In the embodiment 1, the active layer constituting a main portion of theTFT is formed by using a part of a circular semiconductor film includinggrain boundaries which radially extend, for example, a part of thecircular semiconductor 1 as shown in FIGS. 6( a) and 6(b). As shown FIG.6( b), active layers 11 a, 11 b, 11 c are located in such a positionthat the source-drain direction 17 of the active layer (i.e. theelectric current flowing direction 22) approximately coincides with theaforesaid radial direction.

As the result of this, the grain boundary 21 exists along thesource-drain direction 17, that is, the moving direction of electron orhole as a carrier of electric charge, thus the electrical property ofthe TFT becoming good. On the contrary, as active layers 11 d, 11 e asshown in FIG. 6( b) are not active layers according to the embodiment 1,there exists the grain boundary 21 going across the source-draindirection 17 (i.e. the electric current flowing direction 22), thus theaforesaid electrical property is not good.

FIG. 7 is a schematic plan view showing TFTs according to the embodiment1.

In FIG. 7, 32 denotes a source electrode, 33 a drain electrode, 42 acontact hole for electrically connecting the source electrode 32 with asource region 12, and 43 a contact hole for electrically connecting thedrain electrode 33 with a drain region 13. A lot of contact holes 42 and43 are arranged in the source region 12 and the drain region 13 in therespective width directions of them such that the electric current flowsalong the grain boundary 21 with uniform electric current density.

In the TFT 10 as shown in FIG. 7, the width of the source region 12 inthe vicinity of the end portion of the gate electrode 14 is larger thanthe width of the drain region 13 in the vicinity of the end portion ofthe gate electrode 14. The active layer 11 has an approximatelytrapezoid plane shape. Although not shown, the width of the drain region13 in the vicinity of the end portion of the gate electrode 14 may bemade larger than the width of the source region 12 in the vicinity ofthe end portion of the gate electrode 14.

<<Manufacturing Process>>

FIG. 8( a) through FIG. 10( r) are schematic sectional views showing theprocess of manufacturing the TFT according to the embodiment 1.

First of all, as shown in FIG. 8( a), a base oxide film (SiO₂ film) 52with a thickness of 800 nm is formed on a glass substrate 51 formanufacturing a liquid crystal display by means of the plasma CVD methodunder the condition of the substrate temperature of 500° C. and thedeposition time of 40 minutes.

In the next, as shown in FIG. 8( b), an a-Si (amorphous silicon) film 53with a thickness of 100 nm for use in active layer formation is formedby mean of the LP (low pressure)-CVD under the condition of thesubstrate temperature of 450° C. and the deposition time of 70 minutes,during providing Si₂H₆ gas under the condition of the flow speed of 150cccm and the gas pressure of 8 Pa. Then, doping with boron 54 as adopant by means of the ion shower doping method is carried out.

Next, as shown in FIG. 8( c), irradiating by KrF (krypton fluoride)excimer laser light 55 with the intensity of 350 mJ·cm⁻² is carried out.With irradiation by the laser light having a coaxial circular sectionalshape and the intensity made weak at center portion but made strong inperipheral portion, there is obtained a circular polycrystalline siliconfilm 56 (FIG. 8( d)) made up of grains having a large grain size.

Next, as shown in FIG. 8( d), a protection oxide film (SiO₂ film) 57with a thickness of 10 nm is formed by means of the LP-CVD method underthe condition of the substrate temperature of 500° C. and the depositiontime of 10 minutes.

Next, as shown in FIG. 8( e), a patterned resist film 58 is formed byapplying a resist material, and then carrying out exposure anddevelopment of the resist material.

Next, as shown in FIG. 8( f), the protection oxide film 57 and thepolycrystalline silicon film 56 are processed by means of the dryetching method using BCl₃+CH₄ gas, using the resist film 58 as a mask.In this process, the protection oxide film 57 and the polycrystallinesilicon film 56 are processed in the trapezoidal shape (plane shape ofthe active layer 11) as shown in FIGS. 1( a), 1(c), or in the sectorialshape (plane shape of the active layer 11) as shown in FIG. 7.

Next, as shown in FIG. 8( f), the resist film 58 is removed as shown inFIG. 8( g).

Next, as shown in FIG. 9( h), a gate oxide film (SiO₂ film) 59 having afilm thickness of 100 nm by mean of the LP-CVD under the condition ofthe substrate temperature of 500° C. and the deposition time of 60minutes.

Next, as shown in FIG. 9( i), a Mo (molybdenum) film 60 having a filmthickness of 100 nm for formation of a gate electrode is formed by meansof the sputtering method under the condition of the substratetemperature of 100° C. and the deposition time of 10 minutes.

Next, as shown in FIG. 9( j), a patterned resist film 61 is formed byapplying a resist material, and then carrying out exposure anddevelopment of the resist material.

Next, as shown in FIG. 9( k), the Mo film 60 is processed by means ofthe dry etching method using BCl₃+CH₄ gas, using the resist film 61 as amask, thereby the gate electrode 62 being formed.

Next, the resist film 61 as shown in FIG. 9( k) is removed as shown inFIG. 10( l).

Next, as shown in FIG. 9( m), a passivation film (SiO₂ film) 63 having athickness of 200 nm is formed by the plasma CVD under the condition ofthe substrate temperature of 500° C. and the deposition time of 20minutes.

Next, as shown in FIG. 9( n), a patterned resist film 64 is formed byapplying a resist material, and then carrying out exposure anddevelopment of the resist material.

Next, as shown in FIG. 9( o), contact holes 65 are formed by means ofthe dry etching method using CHF₃+O₂ gas, using the resist film 64 as amask.

Next, the resist film 64 as shown in FIG. 9( o) is removed as shown inFIG. 10( p).

Next, as shown in FIG. 10( q), after carrying out the ion doping withphosphoric 66 for forming the source region and the drain region,annealing for dopant activation is carried out for 3 hours in thenitrogen atmosphere of 500° C., thereby forming the source region 67 andthe drain region 68. 69 denotes a channel region located between thesource region 67 and the drain region 68.

Next, as shown in FIG. 10( r), an Al (aluminum) film 70 having athickness of 100 nm for use in electrode formation is formed by means ofthe sputtering method under the condition of the substrate temperatureof 100° C. and the deposition time of 10 minutes.

Next, as shown in FIG. 10( s), a patterned resist film 71 is formed byapplying a resist material, and then carrying out exposure anddevelopment of the resist material.

Next, as shown in FIG. 10( t), the Al film 70 is processed by means ofthe dry etching method using BCl₃+CH₄ gas, using the resist film 70 as amask, thereby a source electrode 72, a drain electrode 73, and a gateelectrode (a take-up electrode from the gate electrode 62) 74 beingformed.

Finally, the resist film 71 as shown in FIG. 10( t) is removed as shownin FIG. 10( u). With this, the TFT 10 is manufactured.

Embodiment 2

FIG. 11( a) is a plan view showing a complementary type circuitapparatus (referred to as “CMOS apparatus herein after)” and FIG. 11( b)is a circuit diagram thereof.

In these figures, 80 denotes a complementary type circuit apparatus, 81a P-type TFT, 82 an N-type TFT, 91 a source electrode connected with thesource region 83 of the P-type TFT 81, 92 an input electrode connectedwith the gate electrodes 84 of the P-type TFT 81 as well as with thegate electrode 85 of the N-type TFT 82, 93 an output electrode connectedwith the drain region 86 of the P-type TFT 81 as well as with the drainregion 87 of the N-type TFT 82, and 94 a source electrode connected withthe source region 88 of the N-type TFT 82.

A lot of contact holes 95, 98, 96, 97 are arranged respectively in thesource regions 83, 88 and the drain regions 86, 87 in the respectivewidth directions of them such that the electric current flows along thegrain boundary 21 with uniform electric current density.

In the P-type TFT 81 of the complementary type circuit apparatus 80 asshown in FIG. 11( a), the width of the source region 83 in the vicinityof the end portion of the gate electrode 84 is larger than the width ofthe drain region 86 in the vicinity of the end portion of the gateelectrode 84. An active layer 89 has am approximately sector planeshape. In the N-type TFT 82 of the complementary type circuit apparatus80, the width of the source region 88 in the vicinity of the end portionof the gate electrode 85 is larger than the width of the drain region 87in the vicinity of the end portion of the gate electrode 85. An activelayer 90 has an approximately sector plane shape.

That is, in the embodiment 2, the N-type TFT 82 and the P-type TFT 81respectively having an approximately sector plane shape are formed on acircular semiconductor film 1 composed of one grain such that they arepoint-symmetrically located at respective points facing to each other,thereby constituting the complementary type circuit apparatus.

In the embodiment 2, as the semiconductor film 1 is composed of onegrain, it becomes possible to obtain the complementary type circuitapparatus 80 having more excellent complementarity comparing with theprior art.

<<Manufacturing Process>>

FIGS. 12( a) and 12(b) are schematic sectional views showing themanufacturing process of the complementary type circuit apparatusaccording to the embodiment 2 of the invention.

In the embodiment 2, the ion doping process as shown in FIG. 10( q) inthe manufacturing process of the embodiment 1, after masking a TFT 81 tobe made P-type with the resist film 76 for preventing it from beingdoped, only a TFT 82 to be made N-type is doped with, for example,phosphor 66 Then, reversely, after masking a TFT 82 to be made theN-type with the resist film 77 for preventing it from being doped, onlya TFT 81 to be made P-type is doped with, for example, boron 78.

After the above doping process, annealing for dopant activation iscarried out for 3 hours in the nitrogen atmosphere of 500° C.

Embodiment 3

In the manufacturing process shown in FIG. 8( c) in the aforesaidembodiment 1, as regards irradiating the a-Si film 53 by KrF excimerlaser light 55 as shown in FIG. 8( c) to obtain a polycrystallinesilicon film 56 (FIG. 8( d)), with irradiation by the laser light havinga coaxial circular sectional shape and the intensity made weak at centerportion but made strong in peripheral portion, there is obtained acircular-shape polycrystalline silicon film 56 (FIG. 8( d)) made up oflarge grains. This polycrystalline silicon film 56 corresponds to thecircular semiconductor film 1 as shown in FIG. 2, FIGS. 6( a), 6(b), andFIG. 7.

FIG. 13( a) is a schematic perspective view indicating anotherirradiation method by KrF excimer laser 55, and FIG. 13( b) is aschematic plan view showing the grain resulting from the aboveirradiation method.

As shown in FIG. 13( a), the irradiation is carried out by KrF excimerlaser light 55 with the intensity of 350 mJ·cm⁻². By adjusting the laserlight intensity to become weak on a center line 75 but to becomestronger in the direction toward the outside, there is obtained, asshown in FIG. 13( b), the polycrystalline silicon film having largegrains 31 extending from a center line 75 in the direction at rightangles thereto. In the semiconductor film having long and slender grains31, the grain boundaries 21 extend in parallel with each other.

FIG. 14( a) is a schematic plan view showing long and slender grains 31as shown in FIG. 13( b), in which grain boundaries 21 extend in parallelwith each other. FIG. 14( b) is a schematic plan view showing severalexamples of arrangement of the active layer 11 in long and slendergrains 31.

In the figure, the more upward the active layer 11 is located, thebetter the electrical property of the TFT including this active layerbecomes. On the contrary, in the figure, the more downward the activelayer 11 is located, the worse the above-mentioned electrical propertybecomes.

That is, in the embodiment 1, the active layer constituting the mainportion of the TFT is a layer made of semiconductor in which grainboundaries extend in parallel to each other. Grains are, for example,long and slender grains 31 as shown in FIGS. 14( a) and 14(b). Activelayers 11 g, 11 h, 11 i, 11 m have an approximately trapezoid planeshape. For comparison, it is shown that active layers 11 f, 11 j, 11 k,11 l have a rectangular plane shape.

The source-drain direction (i.e., electric current flowing direction) ofactive layers 11 f, 11 g, 11 h, 11 i is arranged along the aforesaidparallel direction. With this, as the grain boundary 21 exists along thesource-drain direction 17, that is, the moving direction of electron orhole as a carrier of electric charge, the electrical property of the TFTbecomes good.

As compared with this, active layers 11 j, 11 k, 11 l, 11 m as shown inFIG. 14( b) include the grain boundary 21 going across the source-draindirection at a high rate, the electrical property becomes not good.

When the aforesaid active layer includes one or more grain boundaries,if the active layer is arranged such that the difference between thefollowing two angles becomes 20 degrees or more, one of two angles beingan angle (referred to as “angle regarding the transistor direction”hereinafter) made by one imaginary line connecting the middle positionof the width of the junction face between the channel region and sourceregion with the middle position of the width of the junction facebetween the channel region and the drain region and the other imaginaryline extending in the extending direction of the grain boundary, and theother being an opening angle defined by the width of the junction facebetween the channel region and the source region and the width of thejunction face between the channel region and the drain region, theelectrical property of the TFT becomes good and unevenness in theelectrical property becomes small.

Accordingly, a high performance liquid crystal display can be realizedby using the TFT as described above as a switching device for each pixelin the liquid crystal display, or as a component device of a peripheralcircuits apparatus.

While some embodiments of the invention have been shown and described inthe above with reference to the accompanying drawings, the invention isnot limited to those embodiments. Various changes and modifications willbe naturally possible without departing from the gist of the invention.

1. A thin film semiconductor device, comprising: a substrate; aconductive type semiconductor layer provided on the substrate and havinga trapezoidal planar shape including a long side, a short side, and anopening angle of at least 20 degrees; and a transistor with a sourceregion and a drain region in the trapezoidal semiconductor layer whereineither the source region is on the long side and drain region is on theshort side or the source region is on the short side and the drainregion is on the long side.
 2. A thin film transistor, comprising: acrystallized conductive type semiconductor layer having a trapezoidalplanar shape with a long side, a short side, and an opening angle of atleast 20 degrees; a source region and a drain region provided in thetrapezoidal semiconductor layer, wherein either the source region is onthe long side and drain region is on the short side or the source regionis on the short side and the drain region is on the long side; a gateelectrode provided above or below the semiconductor layer with aninsulating film interposed therebetween; and wherein a channel region islocated between the source region and the drain region and a firstjunction face extends between the source region and the channel regionand has a first junction face width, and a second junction face extendsbetween the channel region and the drain region and has a secondjunction face width, and wherein the first junction face width differsfrom the second junction face width.
 3. A thin film transistor asclaimed in claim 2, wherein the semiconductor layer includes one or moregrain boundaries each of which extends in one of the following twodirections: (1) from the source region to the drain region and (2) fromthe drain region to the source region of the semiconductor layer.
 4. Athin film transistor as claimed in claim 2, wherein the semiconductorlayer includes at least two grain boundaries, each of which extends inone of the following two directions: (1) from the source region to thedrain region and (2) from the drain region to the source region of thesemiconductor layer, and wherein at least two of the grain boundariesare adjacent to each other and extend in-plane with the semiconductorlayer in correspondence with an opening angle.
 5. A thin film transistoras claimed in claim 2, wherein the semiconductor layer includes at leasttwo crystal grain boundaries, each of which extends in one of thefollowing two directions: (1) from the source region to the drain regionand (2) from the drain region to the source region of the semiconductorlayer, the semiconductor layer further including two grain boundariesadjacent to each other and in parallel with an in-plane direction of thesemiconductor layer.
 6. A thin film transistor as claimed in claim 3,further including a first angle formed by a first imaginary lineconnecting the middle of the first junction face width with the middleof the second junction face width and a second imaginary line extendingin the direction of the grain boundary, and a second angle being anopening angle defined by respective imaginary lines connecting firstends of the first junction face width and second ends of the secondjunction face width, wherein the difference between the two angles is atleast 20 degrees.
 7. A thin film transistor as claimed in claim 4,further including a first angle formed by a first imaginary lineconnecting the middle of the first junction face width with the middleof the second junction face width and a second imaginary line extendingin the direction of the grain boundary, and a second angle being anopening angle defined by respective imaginary lines connecting firstends of the first junction face width and second ends of the secondjunction face width, wherein the difference between the two angles is atleast 20 degrees.
 8. A thin film transistor as claimed in claim 5,further including a first angle formed by a first imaginary lineconnecting the middle of the first junction face width with the middleof the second junction face width and a second imaginary line extendingin the direction of the grain boundary, and a second angle being anopening angle defined by respective imaginary lines connecting firstends of the first junction face width and second ends of the secondjunction face width, wherein the difference between the two angles is atleast 20 degrees.
 9. A thin film transistor as claimed in claim 2forming part of a liquid crystal display.
 10. A thin film transistor asclaimed in claim 3 forming part of a liquid crystal display.
 11. A thinfilm transistor as claimed in claim 6 forming part of a liquid crystaldisplay.
 12. A thin film transistor as claimed in claim 2 forming anN-type transistor.
 13. A thin film transistor as claimed in claim 2forming a P-type transistor.
 14. A thin film transistor as claimed inclaim 7 forming part of a liquid crystal display.
 15. A thin filmtransistor as claimed in claim 8 forming part of a liquid crystaldisplay.
 16. A thin film transistor as claimed in claim 2 wherein thegate electrode is configured to cover an entire surface of the channelregion.
 17. A thin film transistor as claimed in claim 3 wherein thegate electrode is configured to cover an entire surface of the channelregion.
 18. A thin film transistor as claimed in claim 4 wherein thegate electrode is configured to cover an entire surface of the channelregion.
 19. A thin film transistor as claimed in claim 2 wherein thesemiconductor layer is formed from an amorphous semiconductor filmcrystallized by a laser beam exhibiting a weaker intensity at its centerthan at its periphery.
 20. A thin film transistor as claimed in claim 3wherein the semiconductor layer is formed from an amorphoussemiconductor film crystallized by a laser beam exhibiting a weakerintensity at its center than at its periphery.